The present invention relates to a method of programming a memory device, and more particularly to a method of programming a multi level cell (hereinafter, referred to as “MLC”) capable of storing data above 2 bits.
Generally, a flash memory device is divided into a NAND flash memory and a NOR flash memory. In the NOR flash memory, each of the memory cells is connected independently to a bit line and a word line, and so the NOR flash memory has excellent random access time. Whereas, in the NAND flash memory, only one contact is required for one cell string because memory cells are connected in series, and so the NAND flash memory has excellent characteristics for integration. Accordingly, the NAND flash memory has been generally employed in high density flash memory.
A well-known NAND flash memory includes a memory cell array, a column decoder, and a page buffer. The memory cell array consists of a plurality of word lines extended along columns, a plurality of bit lines extended along rows and a plurality of cell strings corresponding to the bit lines.
Recently, multi bit cells for storing a plurality of data bits in one memory cell has been actively studied so as to enhance the degree of integration of the above flash memory. This memory cell is referred to as a multi level cell (hereinafter, referred to as “MLC”). A memory cell for storing one data bit is referred to as a single level cell (SLC).
The MLC has at least two threshold voltage distributions, and has at least two stored data states corresponding to the threshold voltage distributions.
Hereinafter, a method of programming data into the MLC will be described in detail.
FIG. 1 is a view illustrating a method of programming a common MLC.
Referring to FIG. 1, a MLC memory cell capable of storing 2 data bits has four data storage states, i.e. [11], [10], [00], and [01]. The distribution of the four data storage states corresponds to the threshold voltage distribution of the MLC. For example, [11] corresponds to the voltage of no more than −2.7V, [10] corresponds to the voltage of 0.3V to 0.7V, [00] corresponds to the voltage of 1.3V to 1.7V, and [01] corresponds to the voltage of 2.3V to 2.7V.
As shown in FIG. 1, a method of storing data in the MLC programs a most significant bit (hereinafter, referred to as “MSB”) and a least significant bit (hereinafter, referred to as “LSB”) of 2 data bits, respectively.
In step S1, the initial MLC state corresponds to [11], this is the erased state and has a threshold voltage of less than −2.7V. The LSB can then be programmed from ‘1’ to ‘0’, which would have a threshold voltage of 0.3V˜0.7V.
In programming the MSB, the threshold voltage is increased to 1.3V˜1.7V as shown in step of S2-1 for data information [00], and the threshold voltage is increased to 2.3V˜2.7V as shown in step of S2-2 for data information [01].
The voltage applied to the MLC when programming data is increased in steps by an incremental step pulse programming (ISPP) method until the memory cell has the desired threshold voltage. Accordingly, the MLC programs the LSB in a first step, and then programs the MSB in a second step.
FIG. 2 is a timing diagram illustrating a programming process based on FIG. 1.
Referring to FIG. 2, a program command PGM COM, an address [Address Input] of a cell to be programmed, data [Data In] to be programmed and a command PGM COM for finishing the program are inputted in a command operation 10 for the program of the LSB.
In the case that the command operation input is finished, a control signal PBPAD of a page buffer is converted from high to low, and the program operation of the LSB is carried out by operation of an internal operation.
When the program operation of the LSB is finished, the steps are repeated for the operation 20 of the MSB.
However, the above method of programming the LSB and the MSB in two steps causes the MLC to be slower than the SLC.